The present invention relates to a pattern inspecting method and a system for use in such a method in which an image or a waveform representing the physical properties of an object such as a semiconductor wafer or the like is obtained by utilizing light, an electron beam or the like, and the image or the waveform is compared with the design information or the resultant image, thereby inspecting a pattern, and a semiconductor wafer manufacturing method employing the same.
As for the conventional method of inspecting a pattern, as described in JP-A-6-294750, there is well known a first method wherein by utilizing the property in which it can be expected that the chips adjacent to one another have the same pattern, a pattern of one chip is compared with that of the chip adjacent thereto, and if there is any difference therebetween, then it is judged that the pattern of any one of the chips has a defect. In addition, as described in JP-A-57-196530, there is well known a second method wherein by utilizing the property in which it can be expected that memory cells within a chip have the same pattern, a pattern of one memory cell is compared with that of the memory cell adjacent thereto, and if there is any difference therebetween, then it is judged that the pattern of any one of the memory cells has a defect.
Further, as described in JP-A-3-232250, there is well known a third method wherein a storage unit for storing therein, on the basis of the pattern arrangement information within a chip, with respect to the scanning direction of a one-dimensional sensor and the storage scanning direction from the starting point of the chip, the data of a chip comparison inspection area and a repeated pattern (a pattern of a memory cell) comparison inspection area is included, and with consideration of both the sensor scanning position and the stage inspection position, it is controlled whether or not the defect output of the chip comparison inspection and the defect output of the repeated pattern comparison inspection can be outputted.
In the conventional first method, two kinds of errors are mixed since the chips have the different patterns as the objects of comparison, and even in the case of the normal portion, the difference occurs so that the identification of the defect of interest to the fine defect becomes difficult. The first error is due to the object. Then, the exposure conditions are different between the different chips because the aligner cannot expose the overall surface of the wafer at the same time, or in the CVD system or the like, the overall surface of the wafer can be processed at the same time, but if the comparison distance is long, then the different thicknesses are obtained in the periphery of the wafer especially so that the different patterns are formed. The second error is due to the inspection system. Then, while the patterns are detected and compared with one another after a predetermined lapse of time because it is difficult to detect a large area at the same time, if the time interval is long, then the detection and comparison are readily to be affected by system drift, vibration and the like. Therefore, in order to ensure the reliability, the system construction will be complicated to increase the cost.
In the conventional second or third method, the pattern of the object to be compared is necessarily present. In other words, the inspection area is limited on the division line between the memories having the comparison direction matching that of the inside of the memory mat portion in which the memory cells are regularly arranged, and also the specification of the area needs to be strictly carried out. In particular, in the recent pattern layout in which the inside of the memory mat is finely divided, the inspection areas need to be set in only the inside of the areas which are obtained by the division. As a result, it will be expected that the area setting takes a lot of time and hence the inspection possible area is limited.
The present invention was made in order to solve the foregoing problems associated with the prior art, and it is an object of the present invention to provide a pattern inspecting method which is capable of inspecting all the areas of portions, which are formed by small scale repetition, on an object to be inspected, such as a semiconductor wafer, with high reliability by the simple specification of the inspection area, and a system for use in such a method.
It is another object of the present invention to provide a method of manufacturing a semiconductor wafer by which, for a semiconductor wafer in which a repetitive pattern including both a memory mat portion and a direct peripheral circuit is formed, a defect can be inspected with high reliability to enable a high quality semiconductor wafer to be manufactured.
In order to attain the above-mentioned objects, according to the present invention, there is provided a pattern inspecting method wherein an object to be inspected, in which a plurality of same pattern groups are formed, is imaged to obtain two-dimensional digital image signals of the object to be inspected; the digital image signals, of the pattern of the pattern group to be inspected on the object to be inspected, out of the two-dimensional digital image signals are compared with the image signals of the patterns of the plurality of other pattern groups on the object to be inspected which should be essentially the same as the pattern of the pattern group to be inspected in order to extract a defect; and the information relating to the defect thus extracted is outputted to a communication line.
In addition, according to the present invention, there is provided a pattern inspecting method wherein an object to be inspected in which a plurality of identical pattern groups are formed at predetermined pitches is imaged to obtain image signals of the object to be inspected; the image signal, of the pattern of the pattern group to be inspected on the object to be inspected, out of the image signals is compared with the image signals of the other pattern groups on the object to be inspected which should be essentially the same as the pattern of the pattern group to be inspected in order to exclude any false defects to detect a true defect; and the information relating to the true defect thus detected is outputted.
In addition, according to the present invention, there is provided a method of inspecting a defect of a pattern wherein a semiconductor wafer in which a pattern including both a memory mat portion and a direct peripheral circuit is repeatedly formed at predetermined pitches is imaged; the image signal which has been obtained by the imaging is converted into digital image signals; the digital image signals corresponding to a notice point of the pattern to be inspected on the semiconductor wafer in the digital image signals which have been obtained by the conversion are compared with a plurality of digital image signals corresponding to th positions which are the predetermined pitches away from the notice point in order to extract defect candidates; false defects are extracted from the defect candidates thus extracted; any of the false defects is excluded from the defect candidates to detect a true defect; and the information relating to the true defect thus detected is outputted through communication means.
Further, according to the present invention, there is provided a method of inspecting a defect of a pattern wherein a semiconductor wafer in which a pattern including both a memory mat portion and a direct peripheral circuit is repeatedly formed at predetermined pitches is imaged; the image signal which has been obtained by the imaging is converted into digital image signals; the digital image signals corresponding to a notice point of the pattern to be inspected on the semiconductor wafer in the digital image signals which have been obtained by the conversion are compared with a plurality of digital image signals corresponding to a plurality of positions in the periphery of the notice point, thereby detecting any of defects which are present in the memory at portion and/or the direct peripheral circuit of the pattern to be inspected; and the information relating to the defects thus detected is outputted.
Further, according to the present invention, there is provided a pattern inspection system including: imaging means for imaging an object to be inspected; A/D conversion means for converting an image signal of the object to be inspected which has been imaged by the imaging means into digital image signals; defect candidate extracting means for comparing the digital image signals of a notice point on the object to be inspected in the digital image signals which have been obtained through the A/D conversion by the A/D conversion means with the digital image signals of comparison points, corresponding to the notice point, of a plurality of pattern which should be essentially the same as the pattern of the notice point in order to extract defect candidates of the notice point; defect detecting means for detecting a true defect from the defect candidates thus extracted; and output means for outputting therethrough the information relating to the true defect thus detracted.
Furthermore, according to the present invention, there is provided a pattern inspection system including: image signal detecting means for detecting the physical quantities of an object to be inspected, in which a repetitive pattern is formed, in the form of two-dimensional image signals; A/D conversion means for converting the two-dimensional image signals which have been detected by the image signal detecting means into two-dimensional image signals; difference image extracting means for comparing the digital image signals of a notice point in the two-dimensional digital image signals which have been obtained through the A/D conversion by the A/D conversion means with the digital image signals of a plurality of comparison points located at predetermined pitches which are integral multiples of the repetitive pitches in the X direction and in the Y direction in order to extract the image signals representing the differences (difference image signals) between the digital image signals of the notice point and the digital image signals of the plurality of comparison points; defect candidate extracting means for extracting defect candidates on the basis of the plurality of difference image signals which have been extracted by the difference image extracting means; and defect extracting means for extracting a true defect from the defect candidates which have been extracted by the defect candidate extracting means.
By adopting the detection method and the system construction as described above, for all the areas of the portions which are formed by the small scale repetition of the pattern, any defect can be inspected with high reliability by the simple area setting method.
In addition, by adopting the above-mentioned system construction, for all the areas of the portions which are formed by the small scale repetition of the pattern, any of defect can be inspected at high speed and with high reliability by the simple area setting method.
Further, by adopting the above-mentioned system construction, for the semiconductor wafer in which the repetitive pattern including both the memory mat portion and the direct peripheral circuit is formed, any defect can be inspected with high reliability and hence the high quality semiconductor wafer can be manufactured.